nam clock ttl Motorola MC68681 ticker and DS1302 RTC ******************************** * Editon History * # Date Comments By * -- -------- ------------------------------------------------ ----- * 10 14/08/02 Converted from mc6840 BdJ * 20 14/08/15 DS1302 RTC added BdJ Edition equ 1 current edition number Typ_Lang set (Systm<<8)+Objct System Object module Attr_Rev set (ReEnt<<8)+0 psect Clock,Typ_Lang,Attr_Rev,Edition,0,ClkEnt use defsfile * settings for 69010SBC board ClkPort set $f00001 base address of mc68681 ClkVect set $1c clock vector irq4 ClkPrior set 1 polling table priority SRA equ $1<<1 ACR equ $4<<1 ISR equ $5<<1 CTUR equ $6<<1 CTLR equ $7<<1 IP equ $d<<1 OPCR equ $d<<1 OPRS equ $e<<1 OPRR equ $f<<1 tck1 equ 1000 number mpu cycles per tick TicksSec equ 50 number of ticks per second ******************************** * Entry point to clock intializtion routine ClkEnt tst.w D_TckSec(a6) is clock already running? bne.s ClkEnt10 skip clock init if so * clock not running, start it up move.w #TicksSec,D_TckSec(a6) set systems tick rate move.b #TicksSec,D_Tick(a6) set tick = ticks/sec * install interrupt in polling table move.l #ClkVect,d0 get vector number move.l #ClkPrior,d1 get priority lea.l ClkSrv(pc),a0 get address of service routine movea.l #ClkPort,a3 get the timer address OS9 F$IRQ put clock on polling table bcs ClkExit move.l #$6a8,$118 patch vector (?) move.w #tck1,d1 ClkEnt10 movea.l #ClkPort,a3 base address duart in a3 move.b #$00,OPCR(a3) config output port of duart move.b #$ff,OPRS(a3) movem.l R$d0(a5),d0-d1 get new date, if any tst.b D_Month(a6) new date/time specified? bne ClkSet if so, set time in rtc * read date from ds1302 rtc move #2000,d1 base year 2000 move.b #$8d,d3 year register bsr rdrtc bsr bcd2int add.b d2,d1 d1 = 0000yyyy lsl.l #8,d1 move.b #$89,d3 bsr rdrtc bsr bcd2int move.b d2,d1 d1 = 00yyyymm lsl.l #8,d1 move.b #$87,d3 bsr rdrtc bsr bcd2int move.b d2,d1 d1 = yyyymmdd * read time move.b #$85,d3 bsr rdrtc bsr bcd2int move.b d2,d0 lsl.l #8,d0 move.b #$83,d3 bsr rdrtc bsr bcd2int move.b d2,d0 lsl.l #8,d0 move.b #$81,d3 bsr rdrtc bsr bcd2int move.b d2,d0 move.l d1,D_Year(a6) os9 F$Julian move.l d1,D_Julian(a6) neg.l d0 calc seconds since midnight add.l #24*60*60,d0 move.l d0,D_Second(a6) bra ClkStart * write time ClkSet movem.l d0-d1/a0,-(sp) save date/time move.b d0,d2 bsr int2bcd move.b #$80,d3 sec bsr wrrtc lsr.l #8,d0 move.b d0,d2 bsr int2bcd move.b #$82,d3 min bsr wrrtc lsr.l #8,d0 move.b d0,d2 bsr int2bcd move.b #$84,d3 hour in 24-format bsr wrrtc * write date move.b d1,d2 bsr int2bcd move.b #$86,d3 day bsr wrrtc lsr.l #8,d1 move.b d1,d2 bsr int2bcd move.b #$88,d3 month bsr wrrtc lsr.l #8,d1 divu #100,d1 swap d1 move.b d1,d2 bsr int2bcd move.b #$8c,d3 year bsr wrrtc movem.l (sp)+,d0-d1/a0 restore date/time in d0/d1 move.l d1,D_Year(a6) os9 F$Julian move.l d1,D_Julian(a6) neg.l d0 add.l #24*60*60,d0 move.l d0,D_Second(a6) addq.l #2,d1 divu #7*256,d1 clr d1 swap d1 divu #7,d1 clr d1 swap d1 addq #1,d1 move.b d1,d2 move.b #$8a,d3 day of the week bsr wrrtc * write trickle charger in ds1302 move.b #$90,d3 register move.b #$a5,d2 1 diode, 2k bsr wrrtc ClkStart move.b #$90,CTUR(a3) 3686400/36864 = 100 move.b #$00,CTLR(a3) move.b #$60,d0 move.b d0,$7c4+1(a6) copy of ACR move.b d0,ACR(a3) set2, timer clk/1 move.b OPRS(a3),d0 start timer move.b #$08,d0 move.b d0,ISR(a3) enable timer interrupt move.b d0,$7c4(a6) copy of IMR ClkExit rts ******************************** * Clock interrupt service routine * Passed: (a2)=global static pointer * (a3)=port address * (a6)=system global data pointer ClkSrv btst #3,ISR(a3) timer irq? beq.s NotClk no, exit move.b OPRR(a3),d0 stop timer: clear interrupt move.b OPRS(a3),d0 start timer move.l D_Clock(a6),a0 jump to system clock routine jmp (a0) NotClk ori #1,ccr rts * * d3 = command, d2 = data read * rdrtc move.b #4,OPRR(a3) CE high moveq #7,d7 rd1 lsr.b #1,d3 shift commandbyte bcc.s rd2 move.b #5,OPRR(a3) io high bsr delay move.b #7,OPRR(a3) clk high bsr delay move.b #2,OPRS(a3) clk low dbra d7,rd1 bra.s rd3 rd2 move.b #1,OPRS(a3) io low bsr delay move.b #6,OPRR(a3) clk high bsr delay move.b #2,OPRS(a3) clk low dbra d7,rd1 rd3 moveq #0,d2 init read byte moveq #7,d7 8 bits rd4 move.b IP(a3),d6 read IP0 lsr.b #1,d6 roxr.b #1,d2 move.b #6,OPRR(a3) clock high bsr delay move.b #2,OPRS(a3) clock low dbra d7,rd4 rd9 move.b #7,OPRS(a3) CE/clk/io low rts * * d3 = command, d2 = data written * wrrtc move.b #4,OPRR(a3) CE high bsr.s wr0 write command move.b d2,d3 bsr.s wr0 write data move.b #4,OPRS(a3) CE/clk/io low rts wr0 moveq #7,d7 8 bits wr1 lsr.b #1,d3 shift bit in carry bcc.s wr2 move.b #5,OPRR(a3) io high bsr delay move.b #7,OPRR(a3) clk high bsr delay move.b #2,OPRS(a3) clk low bsr delay dbra d7,wr1 rts wr2 move.b #1,OPRS(a3) io low bsr delay move.b #6,OPRR(a3) clk high bsr delay move.b #2,OPRS(a3) clk/io low bsr delay dbra d7,wr1 rts delay nop nop rts bcd2int move.b d2,d3 lsr.b #4,d2 andi.l #$f,d2 mulu #10,d2 andi.b #$f,d3 add.b d3,d2 rts int2bcd andi.l #$ff,d2 divu #10,d2 move.b d2,d3 lsl.l #4,d3 swap d2 or.b d3,d2 rts ends Super: